1. Field of the Invention
The present invention relates to a method of crystallizing amorphous silicon, and more particularly, to a method of crystallizing amorphous silicon into polycrystalline silicon and fabricating an array substrate of polycrystalline silicon for a flat panel display device.
2. Discussion of the Related Art
In general, silicon exists as amorphous silicon or crystalline silicon, such as polycrystalline silicon and single crystalline silicon. Amorphous silicon has been used to form the semiconductor layer of a thin film transistor in a liquid crystal display (LCD) device using a glass substrate because it has a low melting point. Therefore, amorphous silicon can be formed into a thin film at a relatively low temperature.
However, LCD devices include a drive integrated circuit (drive IC) to control the thin film transistors in the LCD, and CMOS (complementary metal oxide semiconductor) devices. CMOS devices require polycrystalline silicon for the semiconductor layer because polycrystalline silicon has excellent field effect mobility. In the LCD device using polycrystalline silicon, because the thin film transistor and drive IC are formed on the same substrate and a process of connecting the thin film transistor and the drive IC is not necessary, the number of steps for fabricating the LCD device can be reduced. The thin film transistor using polycrystalline silicon has also been used for an organic electro-luminescent display device.
Polycrystalline silicon can be formed by deposition on a substrate in a polycrystalline state. Alternately, it can be formed by depositing amorphous silicon, such as by plasma enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD), and then crystallizing the amorphous silicon into polycrystalline silicon. There are a number of methods of crystallizing amorphous silicon into polycrystalline silicon, such as, for example, solid phase crystallization (SPC) and excimer laser annealing (ELA).
In SPC, amorphous silicon is deposited on the substrate and then annealed at a high temperature between 500 and 600 degrees Celsius for a relatively long time period. In SPC, since a long time period is required, production yield decreases. Also, when the substrate is large, deformation of substrate can occur through a process of annealing at such high temperatures.
Meanwhile, in ELA, radiation from an excimer laser is irradiated onto an amorphous silicon layer on a substrate for an extremely short time period. This causes the amorphous silicon layer to melt. The melting silicon is subsequently solidified into polycrystalline silicon. However, control of the excimer laser irradiation is technically difficult. Also, production yield is relatively low because only one substrate is treated at a time.
To overcome the problems associated with SPC and ELA, a new method of crystallization, often referred to as metal induced crystallization (MIC), has been used. In MIC, a metal, such as nickel, palladium, or other suitable metal, contacts the amorphous silicon, or the metal is injected into the amorphous silicon at a relatively low temperature between 200 and 500 degrees Celsius. However, the metal remaining in the silicon layer causes electrical leakage from the channel of the thin film transistor.
Recently, a method, without direct contact of a metal and amorphous silicon, often referred to as metal induced lateral crystallization (MILC), has been suggested. In MILC, silicide obtained by reacting a metal and silicon is spread onto a lateral side, and a crystallization of amorphous silicon is sequentially induced. With the MILC method, production yield increases because several substrates are treated in a relatively short time period.
FIGS. 1A to 1E are cross-sectional views of a process of fabricating an array substrate including a thin film transistor using the MILC according to the related art.
As shown in FIG. 1A, a buffer layer 15 is formed on a substrate 11, and an amorphous silicon layer (not shown) is formed on the buffer layer 15 by depositing amorphous silicon. An amorphous silicon pattern 20 is formed by patterning the amorphous silicon layer through a mask process.
As shown in FIG. 1B, a gate insulating layer 25 is formed on the amorphous silicon pattern 20 by depositing an inorganic insulating material. A gate electrode 30 is formed on the gate insulating layer 25 corresponding to a center portion of the amorphous silicon pattern 20 by depositing and patterning a metal.
As shown in FIG. 1C, a doped region 20b and an intrinsic region 20a are defined by doping the amorphous silicon layer 20 with impurities using the gate electrode 30 as a doping mask.
As shown in FIG. 1D, an interlayer insulating layer 40 is formed on the gate electrode 30 and the doped region 20b by depositing an inorganic insulating material. The interlayer insulating layer 40 is patterned to have contact holes 45a and 45b, such that the contact holes 45a and 45b expose respective portions of the doped region 20b. 
As shown in FIG. 1E, a catalyst metal layer 50 is formed on the doped region 20b exposed through the contact holes 45a and 45b and on the interlayer insulating layer 40 by depositing a metal, such as nickel and palladium. Next, amorphous silicon in the doped region 20b covered by the catalyst metal layer 50 is crystallized into polycrystalline silicon by annealing the substrate 11 at a temperature between 300 and 500 degrees Celsius to cause a reaction between the amorphous silicon and the catalyst metal layer 50. Amorphous silicon in the portion of the doped region 20b not covered by the catalyst metal layer 50 and in the intrinsic region 20a is crystallized into polycrystalline silicon using the MIC phenomenon induced by the catalyst metal layer 50.
However, as shown in FIGS. 2A and 2B, the MILC method has several problems. For example, the gate electrode is partially separated from the gate insulating layer in an interface between the gate electrode and the gate insulating layer. A void between the gate electrode and interlayer insulating layer 40 is generated at the side surface of the gate electrode. Accordingly, characteristics of the thin film transistor are deteriorated.
Typically, signal lines including the gate electrode are made of a metal having relatively low resistivity, such as aluminum and aluminum alloy, to decrease signal delay. However, metals having relatively low resistivity are likely to cause the above problems because such metals have low melting points.
As mentioned above, since a quality of the polycrystalline silicon affects the performance characteristics of the thin film transistor, it is important to remove a metal used as a catalyst from the semiconductor layer of polycrystalline silicon. The metal remaining in the semiconductor layer of polycrystalline silicon may be gathered at a surface of the polycrystalline silicon by heating at a temperature between 300 and 500 degrees Celsius, and under oxygen (O2) condition, and the gathered metal is removed by etching or chemical mechanical polishing a part of the surface of polycrystalline silicon.
However, in MILC according to the related art, since the interlayer covers the semiconductor layer of polycrystalline silicon except a portion of the contact hole, it is difficult to effectively remove the catalyst metal in the semiconductor layer of polycrystalline silicon. Furthermore, since the gate electrode of the metal having relatively low resistivity is on the semiconductor layer of polycrystalline silicon, adhesion between the gate electrode and the gate insulating layer is deteriorated.